1. Technical Field
The present invention relates to a test apparatus and a test method. More particularly, the present invention relates to a test apparatus and a test method which adjust a phase difference, between rising and falling signals output from a device under test (DUT), which is caused during transmission of the signals and then obtains the adjusted rising and falling signals. The present application relates to the following Japanese Patent Application.
2. Related Art
FIG. 8 illustrates an exemplary configuration of a test apparatus 10 for testing a device under test (DUT) 400. The test apparatus 10 is disclosed in, for example, Patent Document 1. The test apparatus 10 inputs, into the DUT 400, a test signal which is generated based on a test pattern for testing the DUT 400, and judges whether the DUT 400 passes or fails a test based on an output signal which is output from the DUT 400 in response to the input test signal.
The test apparatus 10 includes therein a period generator 410, a pattern generator 430, a timing generator 420, a waveform shaper 440, a driver 450, a comparator 460, a timing comparing section 470, and a logic comparing section 480. The period generator 410 generates a reference clock which is used as a reference for the operations of the test apparatus 10, based on timing data designated by the pattern generator 430. The period generator 410 also generates a periodic clock which indicates the execution cycle of a test program in accordance with an instruction issued by the pattern generator 430, and supplies the generated periodic clock to the pattern generator 430.
The pattern generator 430 executes a sequence of a test program designated by a user of the test apparatus 10, and generates a test pattern to be supplied to the DUT 400 at each test period that is designated by the periodic clock. The pattern generator 430 also generates an expected value for the output signal that is output from the DUT 400, and supplies the generated expected value to the logic comparing section 480. The timing generator 420 generates, for each test period, a timing of supplying a test signal generated in accordance with a test pattern.
The waveform shaper 440 is a waveform formatter which receives the test pattern from the pattern generator 430, shapes a waveform, and outputs a test signal based on the timing received from the timing generator 420. In other words, the waveform shaper 440 outputs a signal having a waveform designated by the test pattern to the driver 450 at the timing designated by the timing generator 420, for example. The driver 450 supplies the test signal received from the waveform shaper 440 to the DUT 400.
The comparator 460 receives a device output signal output from the DUT 400, and detects whether the device output signal corresponds to the logical value H or L based on the voltage level of the device output signal. The timing comparing section 470 obtains the logical value of the device output signal which is output from the comparator 460 at a designated timing, and outputs the obtained result to the logic comparing section 480. In this way, the timing comparing section 470 outputs, to the timing comparing section 470, a timing comparison result which is obtained by comparing the varying timing of the waveform of the device output signal with the designated timing. The logic comparing section 480 compares the output from the timing comparing section 470 with the expected value. In the above-described manner, the test apparatus 10 can judge whether the DUT 400 passes or fails the test.
[Patent Document 1] Unexamined Japanese Patent Application Publication No. H08-62301
When the test apparatus 10 judges whether the DUT 400 itself passes or falls the test, the timing comparing section 470 is required to obtain, at the same timing, the signals that are all output at the same timing from a plurality of output terminals of the DUT 400. Even though the DUT 400 outputs the signals at the same timing, however, the signals arrive at the timing comparing section 470 at different timings due to various factors including a variance, among the output terminals, in terms of the path length from the DUT 400 to the timing comparing section 470. Therefore, the timing comparing section 470 needs to absorb the variance in timing.
Similarly, the path length between the DUT 400 and timing comparing section 470 or the logical elements cause a difference between a time from when the DUT 400 outputs a rising signal to when the rising signal arrives at the timing comparing section 470 and a time from when the DUT 400 outputs a falling signal to when the falling signal arrives at the timing comparing section 470. Therefore, the timing comparing section 470 needs to perform a timing adjusting operation so as to be capable of obtaining, at the same timing, the rising and falling signals that are output from the DUT 400 at the same timing.